Remote control system having command and address signals

ABSTRACT

A signaling system located at a central station sequentially interrogates a plurality of remotely located transponders. Means are provided for interrupting the normal addressing sequence and for commanding the operation of any one of eight relays at any selected remote station.

Unite States Patent [1 1 [111 3,882,465

Cook et al. May 6, 1975 [54] REMOTE CONTROL SYSTEM HAVING 3,634,8241/1972 Zinn 340/167 A COMMAND AND ADDRESS SIGNALS 3,806,872 4/1974 Odom340/167 A [75] Inventors: Charles W. Cook; James T. Odom,

both of Huntsville, Ala. Primary Examiner-Harold I. Pitts [73] Assignee:Avco Corporation, Huntsville, Ala. Agent or Flrmwchafles Hogan;

[22] Filed: Dec. 5, 1973 [21] App]. No.: 421,901

[57] ABSTRACT U-S- Cl. A ig li g y t l d t a t l t ti q [51] [1.1L Cl.H044] 9/00 tially interrogates a plurality f remotely located tran [58]new of Search 340/147 167 sponders. Means are provided for interruptingthe nor- 340/152 164 R ma] addressing sequence and for commanding the0peration of any one of eight relays at any selected re- [56] ReferencesCited mote Station.

UNITED STATES PATENTS 1 3,518,628 6/1970 Giel 340/163 X 12 Claims, 12Drawing Figures I7- CONTROLEE l7- CONTROLEE I7- CONTROLEE MONITORS -I4MONITORS I4 MONITORS -I4 REMOTE REMOTE REMOTE STATION STATION STATIONCENTRAL STATION 19.

1 I6 l6 I6 DISPLAY DISPLAY DISPLAY PAIENIEDHIY' ems 3.882.465

sum 10$ 5 l7- CONTROLEE I7 CONTROLEE I7- CONTROLEE MONITORS I4' MONITORS-l4 MONITORS I ,12 I2 l ,2

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SUMMARY OF THE INVENTION This invention provides for the electronicalteration of an address code in a transponder-type security system toremotely control equipment at the transponder location. In a previouslyexisting system an address signal, herein sometimes called the ABCDaddress, causes a transponder to transmit its existing status back tothe central station. This invention provides simple means that permitsthe performance of various functions at the remote station. This isaccomplished by altering the address signal by inserting a command codeahead of it. We sometimes herein refer to the command code as the WXYZcommand or the MN command.

The normal ABCD address comprises a burst of pulses A, a space B, aburst of pulses C, and a space D. Similarly, the WXYZ command is made upof a burst of pulses W, a space X, a burst of pulses Y and a space Z,while the MN command is made up of an M pulse and an N space. Whendemodulated, the various signals are square waves and for convenienceare sometimes described as such.

When the transponder or other auxiliary device at a remote locationdecodes a proper command and when it decodes a proper address, a relaywill open or close. The auxiliary device added at the remote transponderis referred to in this specification as a controlee. Each controlee haseight relays associated with it and depending on the command code, anyone or all of the eight relays can be energized or some other functioncan be performed. Four controlees can be selectively controlled. Thewidths of the pulses and spaces of the address and command codes arechosen such that the command decoder will not be acted on by the ABCDpulses, and the address decoder will not be acted on by WXYZ or MNpulses.

THE DRAWINGS FIG. 1 is a block diagram showing a transponder system inwhich the disclosed invention is utilized;

FIGS. 2a, 2b, and 2c are curves showing the nature of the codedtransmitted address signal and command signals;

FIG. 3 is a curve showing the nature of the coded transponded signal;

FIG. 4 is a block diagram showing the interrupter system disclosed inOdom application Ser. No. 358,862, and modified for use in accordancewith this invention except that for the purpose of simplification, itdoes not embody the means for generating the MN command;

FIG. 5 is a block diagram showing the transponder with the addition of acontrolee;

FIG. 6 is a block diagram of the controlee;

FIG. 7 is a series of curves illustrating the operation of thecontrolee;

FIG. 8 is a series of curves showing the operation of the timing shiftregister;

FIG. 9 shows the system for generation of the MN command; and

FIG. 10 is a series of curves showing the operation of the MN commandportion of the system.

The overall system is shown schematically in FIG. 1. A central station10 sends to the remote stations 12 a series of tone pulses whichrepresent the remote station address. Each of the particular remotestations 12 (of which there may be any number within the timecapabilities of the system) responds to a particular interrogation bytransmitting back to the central station tone pulses of lengths that aredetermined by the status and changes of status of the respectivemonitors 14 connected to it. Having received the responses from theremote station, the central station decodes the response, processes theinformation and displays it in displays 16 in a manner described in US.Pat. No. 3,634,824, and in US. Pat. application Ser. No. 359,238. Inaddition each remote station 12 is provided with a controlee 17 whichfunctions, on command from the central station, to perform a pre-wiredfunction, for example, to activate or deactivate a particular monitorequipment.

The addresses of the remote stations are contained in a fixed frequencysignal of the type shown in FIG. 2a. As shown, the central stationtransmits a first fixed frequency signal A having a duration T1. This isfollowed by a space B which occurs for a period T2. The space B is thenfollowed by another signal C of the same fixed frequency and having atime period T3 which is then followed by a space D having a period T4.The address of the remote station is coded into the transmission byvarying each of the time periods T1, T2, and T3. The time period T4 is afixed period during which the remote station transponds. Theoreticallythe number of addresses may be multiplied by adding additional timeperiods, all of which may be variable. In a practical system, only thetimes T1 and T2 were variable to provide a combination of 25 addresses.When a function is to be performed by a controlee 17, the normal addresssequence is interrupted, the address signal is delayed, and a WXYZcommand signal is transmitted. As shown in FIG. 2b, the command signalprecedes the address signal.

As indicated in FIG. 1, each of the remote stations may contain a numberof monitors 14. Certain of the monitors may, for example, be arranged todetect the opening of a window, the breaking of a window, the walking ona floor, a fire, or the opening of a door. Each of these conditions isgiven a priority level. As shown in FIG. 3, a remote station transmits asingle frequency back to the central station and it will have a durationdetermined by the highest level alarm that is causing a transmission.The first period t, of the transmission occurs at every interrogation togive a positive indication that the transponder is operative. A level 0priority alarm has a duration t a level 1 priority alarm will have aduration t and so forth, so that the highest level alarm signal willdominate all transponded signals. The means for generating an alarm isdescribed in detail in U.S. Pat. application of Odom, Ser. No. 358,862and is not repeated here.

When an indication appears at the central station that an alarm is beingtransmitted by the remote station, it is desirable to interrupt thenormal sequence, and re-interrogate the station from which an alarm isindicated and then display or otherwise read out the particular cause ofthe alarm. The block diagram in FIG. 4 shows schematically how theaddresses to the remote stations are sequentially coded and transmitted,and also how the normal sequence is interrupted. As will also be seen,the interruption of the normal signal provides the means for delayingthe ABCD address and preceding it with a WXYZ command or an MN command.

As shown in FIG. 4, the transmission system includes a fixed frequencyoscillator 20 which transmits a signal to the remote stations wheneverits associated AND gate 22 is enabled. The AND gate 22 is enabled onlywhen it receives the output from an OR gate 24 in addition to the outputsignal from the oscillator 20.

To control the output from the OR gate 24, and therefore to permit theintroduction of the appropriate addresses for the remote stations, aplurality of oneshots 26, 28, 30, and 32 are connected in series, thatis, the one-shots are arranged so that the trailing edge of one triggersthe next. It will be noted that the response one-shot 32 is coupled tothe one-shot 26 through an AND gate 33 and an OR gate 37. The output ofeach of the one-shots is a square wave having a duration determined bythe time constants which are set in. The one-shot 32, referred to as theresponse oneshot, has a fixed time constant so that the duration T4 ofits output remains fixed. The time constants of the one-shots 26, 28,and 30 are alterable, sequentially or manually, and the durations of theoutputs from these one-shots determine the time periods T1, T2 and T3shown in FIG. 2a. These four one-shots provide the ABCD address code.

Under normal conditions, the time constants of the one-shots 26, 28, and30 are changed by sequentially and cyclically introducing differentvalues of resistance into their respective R-C circuits. This isaccomplished by means of conventional sequential switching circuits 34,35, and 36.

The sequential switching circuits 34, 35, and 36 have a number ofstages, each one of which sequentially connects a different resistorvalue into a respective oneshot R-C network through an associatedaddress selector circuit 38, 40, and 42. The update clock for thesequential switching circuit 34 is the output pulse from the responseone-shot 32. After the last stage of the switching circuit 34 isactivated, the next update pulse resets it to the first stage andupdates sequential switching circuit 35. Similarly, the resetting of thesequential switching circuit 35 updates the switching circuit 36. Thismeans that if there are five stations in each switching circuit, thereis a possibility of having 125 different addresses. In a system asreduced to practice, there were five stages in the circuit 34 and fivestages in the circuit 35 and only a single stage in the circuit 36, sothat a total of 25 addresses were possible. The particular resistorselected by the switching circuit 34 is connected into the one-shot 26through address selector 38, the resistor selected by the circuit 35 isconnected to one-shot 28 through the address selector 40, and theresistor selected by the switching circuit 36 is connected into theone-shot 30 by the address selector 42. As described in detail in saidOdom application, the response one-shot 32 provides the update pulse forthe sequential switching circuit 34 through an interrupt circuit 44. Forreasons hereinafter explained, the output from the response one-shot isdeveloped through the AND gate 33. It is applied to the one-shot 26through the OR gate 37.

A particular ABCD address is selected by manually setting certain timeconstants into the address selectors 38, 40, and 42 through terminals46, 48, and 50 and interrupting the sequencing of the switching circuits34, 35, and 36. As explained in detail in the Odom application, apreselected resistor establishes the time constants of the one-shots 26,28, and 30 to code the selected address for transmission.

To transmit a command to a selected address, this invention provides forthe delay of the ABCD address signal and for the insertion of a WXYZcommand. The same oscillator 20, AND gate 22, and OR gate 24 used togenerate the ABCD address are also used to generate the WXYZ command.However, for the purpose of generating the command, the OR gate 24 isalso controlled by a series of one-shots 49, 51, 53, and 55. The outputof one-shot 49 provides the W pulse which is applied to the OR gate 24through OR gate 47. The oneshot 51 provides the X space. The one-shot 53provides the Y pulse which is applied to the AND gate 22 through the ORgates 47 and 24. The one-shot 55 provides the Z space. The time constantfor each of the one-shots 49, 51, 53, and 55 is provided, respectively,by command selectors 57, 59, 61, and 63, the particular command beingset in at the terminals 58, 60, 62, and 64. The command system operatesin the same manner as the address system, that is to say, the output ofeach of the one-shots is a square wave having a duration determined bythe time constants which are set in and each is connected in series,that is, they are arranged so that the trailing edge of one triggers thenext.

As previously noted, the ABCD address is delayed so that the WXYZcommand can be inserted ahead of it. For this purpose we provide an ANDgate 65 having an input terminal 67 to which an initiate command isapplied in the form of a direct voltage. The second input terminal ofAND gate 65 is supplied with the output of the response one-shot 32.

The initiate command pulse is also applied to a latch 69, the Q outputof which is normally a logical l. Upon the application of the initiatecommand pulse to the set input terminal of latch 69, the Q outputterminal of the latch 69 is changed to a logical 0. No output can thenbe developed from the AND gate 33 when it receives the next output pulsefrom the response one-shot 32. When the AND gate 33 has a logical O atone of its input terminals, the output from the response one-shot 32cannot update the one-shot 26, so that any address which has beeninserted into the address selectors 38, 40, and 42 cannot betransmitted.

Since the output pulse of the response one-shot 32 is also applied tothe second input terminal of the AND gate 65, an output pulse isdeveloped at the output terminal of the AND gate 65. This pulse isapplied to the interrupt circuit 44 so that the normal address switchingis interrupted. The same pulse is also applied to the W one-shot 49 sothat a WXYZ command signal is initiated and transmitted from theoscillator 20 through the AND gate 22 to the remote stations.

The trailing edge of the output of the Z one-shot 55 triggers a one-shot71 which is connected to the reset terminal of latch 69, therebyre-establishing a logical l at the Q output and in addition is appliedthrough the OR gate 37 to the one-shot 26 to begin the cycling of theaddress one-shots 26, 28, 30, and 32. Upon the completion of that cyclethe response one-shot recycles the system through the normal sequenceswitching cycles.

The operation of the remote stations is shown generally in FIG. 5. Thesignal from the central station is applied from the telephone linesthrough an interface 73,

' and filter 75 and an amplifier 77. The signal from amplifier 77comprises the series of pulses shown in FIG.

2a if no command is given or in FIG. 2b if a command is included. Thesignal is then applied to a demodulator 79, the output of which is asquare wave of the envelope of the curves shown in FIGS. or 2b. In theabsence of the WXYZ command signal, the decoder 81 serves to decode theABCD address signal, and as described in the aforesaid Odom application,enables the generation of an output pulse from status one-shots 83. Theoutputs from the status one-shots 83 will be a pulse having a durationdepending upon the status of the various sensor inputs applied to thevarious input terminals 0, 1, 2, and n. This pulse provides one input toan AND gate 85, the other input of which is supplied by an oscillator87. The output from the AND gate 85 is therefore a burst of pulseshaving a duration representing the level of the sensor which isproviding an input for transmission back to the central station throughthe interface 73. If an WXYZ command appears in the output of thedemodulator 79, then it is decoded ahead of the ABCD address in thecontrolee 17 to control the energiation of any of a group of eightrelays 81.

The controlee for selectively operating any one or all of eight relaysis shown in FIG. 6. Each of the relays 81 is represented as a relay coil81 in the collector-emitter circuit of a transistor 82, the base ofwhich is biased by a binary voltage applied through a resistor 84. Whileonly one relay coil and transistor is shown, it will be understood thateight such sets are provided, one connected to each of a group of eightflip-flops 86a-h. The relays are turned on or off by selectively settingor resetting any one or all eight of the flip-flops 86a-h.

The flip-flops 86ah are selectively set by the outputs from a set of ANDgates 88a-h. When a particular AND gate 88a-h is enabled, a respectiveflip-flop changes state to energize or de-energize a relay.

A second set of AND gates 90a and 90b are each used to enable half ofthe AND gates 88a-h. That is to say, when the AND gate 90a is enabled, alogical l is applied to one input terminal of each of the AND gates 88a,c, e, and g, and when the AND gate 90b is enabled, a logical l isapplied to one of the input terminals of each of the AND gates 88b, d,f, and h.

The AND gates 90a and 90b are enabled by two inputs, one from theoutputs of flip-flops 92a and 92b, respectively, the other from theoutput of a one-shot 83 (also see FIG. 5). If the AND gate 90a isenabled, then each of the four AND gates 88a, 0, e, and g has a logicall on one of its inputs. One of those four is selected by the flip-flops94ab, 940d, 94ef, or 94gh. For example, if a logical 1 is developed onthe output of 94ab at the same time that a logical l is developed at theoutput of AND gate 900, the AND gate 88a will be enabled and theflip-flop 86a will change state. On the other hand,

if the flip-flop 92b changed state, the AND gate b would be enabled bythe output of the one-shot 83 and hence the AND gates 88b, d, f, and itwould be enabled, depending on the status of the four flip-flops 94ab togh.

The logic of the WXYZ code as applied to this system is as follows:Every W pulse has a duration of one or two time units. Every X space hasa duration of l, 2, 3, or 4 time units. Every Y pulse has a duration ofone or-two time units, and every Z pulse has a duration of l, 2, 3, or 4time units. In a practical system each unit of time was equal to 12milliseconds, and for purposes of convenience that duration will bediscussed in the following examples.

The purpose of the W pulse is to arrange the logic of the flip-flops86a-h so that on completion of the command, a relay which is on can beturned off, or a relay which is off can be turned on. The purpose of theX space is to select one of four controlees, in this case controlee N0.3. The purpose of the Y pulse is to enable either an AND gate 96a or anAND gate 96b, depending on the duration of the Y pulse. The AND gates96a and 96b set either the flip-flop 920 or 92b which in turn enablesAND gates 90a or 90b to supply a logical l to four of the gates 88a-h.The purpose of the Z pulse is to select a particular one of the four.

The received WXYZ command and ABCD address are applied to a pulse shaper100. The wave train envelope at the output of pulse shaper 100 of thetransmitted pulses is developed, as shown in FIG. 7. The output of thepulse shaper 100 is then applied to an edge differentiator 102 whichdevelops a series of leading and trailing edge pulses b. The pulses bprovide the logic for the operation of the gates.

The pulses b are applied to one-shots 104 and 106 which develop outputpulses c and d. The output pulses c are supplied to a clock 108 which isdesigned to operate at a 12 millisecond rate; i.e., the clock generatesa 6-millisecond pulse followed by a 6-millisecond space (pulse e, FIG.7). The pulses c serve to synchronize the operation of the clock withthe WXYZ command. The pulses e are used to advance a timing shiftregister 1 10. The pulses a from the one-shot 106 are used for resettingthe timing shift register 110.

The timing shift register 110 contains conventional binary circuitswhich serve to generate sequential output timing pulses I, II, III, andIV (see FIG. 8) at the output of its stages 1, 2, 3, and 4,respectively. Each positive going timing pulse e lasts 6 milliseconds.The pulse at output terminal 1 occurs 6 milliseconds after reset bypulse d. The pulses II, III, and IV sequentially follow the pulse I. Forexample, in the illustrated WXYZ command, the W pulse is 24milliseconds, and therefore a l2-millisecond output pulse will bedeveloped at terminal 1 and then at terminal 2. Further, since space Xis 48 milliseconds, l2-millisecond output pulses will be developedsequentially at terminals 1, 2, 3, and 4, the pulse I extending from6-18 milliseconds, the pulse II from 18-30 milliseconds, the pulse IIIfrom 30-42 milliseconds, and the pulse IV from 4254 milliseconds. (Thetimes above stated ignore the width of the b pulses.)

The output pulses b from the edge differentiator 102 are also appliedthrough a series of gates (to be described) to the input terminal 112 ofa pulse shift register 114. Initially (i.e., after reset) the pulseshift register has an output at stage W. Each pulse b applied to theinput terminal 112 advances the pulse shift register 114 once. Since thepulses b represent the beginnings and ends of the WXYZ command, alogical 1 will appear at the W stage during the generation of the Wpulse, a logical 1 will appear at the X stage during the generation ofthe X space, a logical 1 will appear at the Y stage during thegeneration of a Y pulse, and a logical 1 will appear at the Z stageduring the generation of the Z space. The end of the Z space (thebeginning of the ABCD address) serves to reset the register 1 14 to itsW stage.

To describe the system of gates and the relationship between the timingshift register 1 10 and the pulse shift register 114, we will assumeparticular WXYZ commands. First, let us assume that a W pulse is oneunit in width, or 12 milliseconds. In such a case the output pulses bfrom the edge differentiator 102 will provide a logical 1 to an inputterminal of several AND gates 118, 120, 122 and 134.

The AND gate 116 will be enabled only if its two other input terminalsare provided with logical ls. One of the input terminals will have alogical 1 if the timing shift register has a logical l at its firstterminal. Such a condition will occur if the trailing edge of the Wpulse occurs 12 milliseconds after the leading edge. The other terminalwill be provided with an enabling pulse from the W stage of the pulseshift register if the register has not otherwise been advanced. Thismeans that if the W pulse is 12 milliseconds long, the AND gate 116 willbe enabled and it will provide an output pulse to the on terminal of aflip-flop 124 causing the flipflop 124 to change state, enabling theflip-flops 86a-h so that the pulse output of one of the gates 88a-h canturn one of the relays 81 on, if it has been off.

Assume now that the W pulse is 24 milliseconds, or 2 units long. Asbefore, the pulse b occurring at the trailing edge of the W pulseprovides a logical 1 for one input of AND gate 116. In addition, sincethe pulse shift register 114 is in its initial W state, the gate 116 isprovided with a second logical 1. However, since the W pulse is 24milliseconds long, the timing shift register 110 will have been advancedto its second output terminal so that the third input terminal of ANDgate 116 is not enabled, and an output pulse is not developed from theAND gate 116. This means that the flip-flop 124 remains in its initialstate, and therefore the next enabling pulses to one of the gates 88a-hwill serve to turn a particular relay off, if it has been on.

The pulse b occurring at the trailing edge of the W pulse is applied toan AND gate 120. If AND gate 120 is otherwise enabled, then it developsan output pulse through an OR gate 125 which supplies a pulse to theinput terminal 112 and advances the shift register 114 to the X stage.The AND gate 120 is enabled at one of its input terminals through an ORgate 126 with logical 1 existing at the W stage of the pulse shiftregister 114. Another terminal of the AND gate 120 is enabled throughthe OR gate 128 with the logical 1 output of the first stage (if the Wpulse is one unit) or the second state (if the W pulse is two units) ofthe timing shift register 110. Thus, upon the occurrence of the pulse bat the trailing edge of the W pulse, the pulse shift register 114 isadvanced to the X stage. The pulse 0 generated at the trailing edge ofthe W pulse resets the timing shift register to 0.

Next assume that the X space is 36 milliseconds. (It could also be 12,14, or 48 milliseconds, but this illustrated system can only decode an Xpulse if it is 36 milliseconds, because the switch 133 is connected tostage 3 of the timing shift register.) A 36-millisecond X space willcause the timing shift register 1 10 to advance to its third stage and alogical I is applied through the switch 133 to one input terminal of theAND gate 134. The second terminal of the AND gate 134 is connecteddirectly with the logical 1 output from the X stage of the pulse shiftregister 114. Therefore, the pulse b occurring at the leading edge ofthe pulse Y passes through the enabled AND gate 134 and the OR gate 124to the input terminal 112 of the pulse shift register 114, therebyadvancing the pulse shift register to the Y stage. The output pulse coccurring at the leading edge of the Y pulses resets the timing shiftregister to 0 so that the system is now ready to analyze the Y pulse.(Note that with the switch 133 rotated to connect to any other stage ofregister 110, it could not have decoded a 36-millisecond X space.)

Now assume that the Y pulse is 24 milliseconds. The clock 108 advancesthe timing shift register 110 to its second stage from which a logical 1is supplied to one input terminal of AND gate 96b. Moreover, the logical1 appearing at the Y stage of the pulse shift register 1 14 is alsoapplied to the AND gate 96a. Thus, AND gate 96b is enabled to change thestate of the flip-flop 92b to provide a logical 1 output for one inputterminal of the AND gate b. Had the W pulse been 12 milliseconds, theAND gate 96a would have been enabled and the flip-flop 92a would havechanged state to provide a logical l for the AND gate 90a.

The logical 1 at the second stage of the timing shift register is alsosupplied through the OR gate 128 to one terminal of the AND gate 120. Asecond terminal of the AND gate is supplied through the OR gate 126 withthe logical 1 from the Y stage of the pulse shift register 114. Thepulse b occurring at the trailing edge of the Y pulse passes through theAND gate 120 and the OR gate to the input terminal 112 of the pulseshift register 114 so that the register is advanced to its Z stage. Atthe same time the c pulse resets the timing shift register 110 to 0 andthe system is now prepared to analyze the Z space.

Now if the Z pulse is 48 milliseconds (it could also be 12, 24, or 36milliseconds), a logical 1 appears at the fourth stage of the timingshift register 110 and a logica] 1 is supplied through the OR gate 130to one input of the AND gate 118. Moreover, the logical l at the Z stageof the pulse shift register 114 is applied through OR gate 132 to asecond input terminal of AND gate 118. The Z output stage also suppliesa logical l to one terminal of each of the AND gates 98a-d. A secondterminal of each of the AND gates 98a-d is also supplied with thelogical bs, pulses I, II, III, and IV appearing sequentially at each ofthe stages of timing shift register 110. The occurrence of a pulse b atthe end of the Z space coincides with pulse IV and therefore the leadingedge of the ABCD address passes through both the AND gate 118 and theAND gate 98d. This changes the state of flip-flop 94gh to provide alogical 1 for one terminal of AND gate 88h. It also advances the pulseshift register 114 to its W stage.

Now, upon the occurrence of a response from a proper ABCD address, asdescribed in detail in the Odom application, a response pulse isgenerated in the one-shot 83. This pulse passes through AND gate 90b and88h to change the state of flip-flop 86h and turn its associated relayon or off. Following the pulse from the one-shot 83, a second one-shotpulse is generated by a one-shot 135. This pulse is applied through anOR gate 137 to the off terminal of the flip-flop 124, which is now readyfor a new command.

The MN command serves to turn one or all of the relays on each controleeon or off simultaneously. FIG. 9 when added to FIG. 4 shows the meansfor generating the MN command pulse. As shown, the system incorporatestwo switches 139 and 141 which selectively connect the initiate commandpulse at terminal 67 through the AND gate 65 to either the WXYZoneshots, or the MN one-shots. With the switches 139 and 141 in theposition shown in FIG. 4, the OR gate 24 is controlled by the WXYZone-shots 49, 51, 53, and 55. With the switches in the position shown inFIG. 9, the OR gate 24 is controlled by MN oneshots 143 and 145.

The output of the one-shot 143 provides the M pulse which is applieddirectly to OR gate 24. The one-shot 145 provides the N space which isapplied to one-shot 71. The time constant for the one-shots 143 and 145is provided, respectively, by command selector 147 and 149, theparticular command being set in at terminals 151 and 153. The output ofeach of the one-shots is a square wave having a duration determined bythe time constants which are set in and the trailing edge of the M pulsefrom the one-shot 143 triggers the N one-shot 145. The MN command thenfunctions in the same manner as WXYZ command, and is transmitted to theremote stations ahead of the ABCD address. However, the controlee isindependent of the ABCD address, and the relays operate independently ofa response to an address code.

The M pulse may have one or two widths, for example 450 and 650milliseconds. If it is 450 milliseconds, it may be used to close one ormore of the relays 81, and it will also close similar relays of othercontrolees. If it is 650 milliseconds, it is used to open each of therelays 81. The N space is 650 milliseconds. While these particular timeswere used in a practical application of the invention, it will berecognized that other times may also be used so long as they do notprovide a conflict with the WXYZ pulses or with the ABCD pulses.

The MN pulses are ahead of the delayed ABCD pulses and are applied tothe pulse shapers 100 at the remote stations (see FIG. 6). The squarewave output of the pulse shaper 100 (see the curves 1 and 2 in FIG. 10)is applied to one input of an AND gate 160, the other input of which issupplied with the 6-millisecond pulses of the clock 108. The output fromthe AND gate 160 is applied to a counter 162. The counter 162 has twooutput stages 01 and 02. The logic of the counter is such that a logicalO is on its output terminal 01 except during the time interval from384-576 milliseconds when it is a logical 1 (see curve 2 in FIG. 10).Similarly, a logical is at the output terminal 02 except during theinterval from 577-768 milliseconds (see curve in FIG. The output atstage 01 is applied to AND gate 164 while the output at stage 02 isapplied to AND gate 166.

The output from the pulse shaper 100 is also applied to the edgedifferentiator 102 which, as before, produces pulses b at the leadingand trailing edges of the M and N pulses (see curves 3 and 6 in FIG.10). The pulses b are applied to both AND gates 164 and 166. If a pulseb occurs when a logical l is present at output stage 01, an on pulse isgated through AND gate 164 to one or more of the flip-flops 86ah. If a bpulse occurs when a logical l is present at stage 02, then an off pulseis applied through the AND gate 166 to one or more of the flip-flops86a-h. Note that while only one such flip-flop 86h is shown connected tothe on-off lines, the invention contemplates the connection of one ormore of the flip-flops 86ah across such lines so that all of the relays81 may be turned on or off simultaneously.

The MN pulses generated for the purpose of turning all the relays on oroff are not decoded in the WXYZ decoder, since the pulses b do not occurat the programmed times and the WXYZ decoder is automatically resetwithout activating any of the relays 81. Upon the generation of thefirst pulse b, the pulse shift register is at its W stage and it cannotbe shifted until the end of the M pulse when a second pulse b isgenerated. Since the logic of the WXYZ decoder is such that a W pulsemust occur within 24 milliseconds, this means that there will be nological l in the timing shift register that will be applied to either ofthe OR gates 128 and 130, and therefore no advance pulse can bedeveloped for the pulse shift register 114. The absence of an advancepulse means there will be a logical 0 at the input of an inverter 168,and the output of the inverter 168 supplies a logical l to the input ofAND gate 122. The occurrence of pulse b when applied to the other inputof AND gate 122 develops a reset pulse for the pulse shift register sothat the system is returned to its initial state (or maintained in itsoriginal state) if the timing of the WXYZ pulses is not as programmed.

Reset also occurs after a proper decoding and response. The same resetpulse applied to the pulse shift register is also applied to one inputof an AND gate 170. The other input of an AND gate 170 is suppliedthrough an inverter 172 with the output from the Z state of the pulseshift register 114. If the Z state is at logical O, a logical l istherefore applied to the AND gate 170 through the inverter 172 and theoccurrence of a reset pulse from the AND gate 122 is then appliedthrough the OR gate 137 to the off input terminal of flip-flop 124.

We claim:

1. In a signaling system having a central station and a plurality ofremote transponding stations, the combination comprising:

signal transmitting means at said central station for transmitting codedaddress signal to said remote stations;

an address decoder at each of said remote stations for decoding aparticular one of said coded address signals;

means responsive to the decoding of a particular one of said addresssignals for generating a response signal to said central station;

command means at said central station for transmitting a coded commandsignal ahead of a selected address signal;

a command decoder at each of said remote stations for decoding saidcommand signals; and

means responsive to the decoding of said command signals and thegeneration of said response signal for generating a response to saidcommand signal.

2. The invention as defined in claim 1 wherein said signal transmittingmeans transmits said coded address signals in a preestablished sequence;and

wherein said command transmitting means includes means for interruptingand delaying said sequence until the transmission of said command signaland a selected address signal are completed.

3. The invention as defined in claim 2 wherein said address and commandsignals are duration coded pulses, said command decoder comprising aplurality of gates, said plurality being equal to the number of commandsignals, said gates each having an output connected to a respective loadand having first and second inputs, each of said first inputs beingsupplied with a pulse by only one decoded command signal, said secondinput being enabled by said response signal.

4. The invention as defined in claim 1 wherein said command signal andsaid address signal each comprises a plurality of pulses and spaces eachhaving a coded duration, the first pulse of said address signalimmediately following the last space of said command signal, and whereinsaid command decoder comprises:

means for generating a short duration pulse at the leading and trailingedges of each of said pulses;

a clock for generating timing pulses, said clock being synchronized bysaid short duration pulses;

a timing shift register having a plurality of outputs, each of saidoutputs representing one possible coded duration, said timing shiftregister being advanced by the timing pulses of said clock;

a pulse shift register having a plurality of outputs equal to the numberof pulses and spaces of said command signal, said pulse shift registerbeing advanced by each of said short duration pulses whereby each outputrepresents a particular pulse or space; and

a system of gates, a selected one of said gates being enabled inresponse to one preselected combination of the outputs of said pulseshift register and said timing shift register, and a response to saidaddress signal.

5. The invention as defined in claim 4 wherein said command decoder alsocomprises first and second gates, the outputs from said gates serving toinitiate or terminate a function, said first gate being enabled when theduration of said command signal is equal to a first predetermined periodof time substantially greater than said coded duration, said second gatebeing enabled when the duration of said command signal pulse is equal toa second such predetermined period of time, whereby a function maysimultaneously be performed at all remote stations.

6. The invention as defined in claim 4 wherein said command decoder alsocomprises a counter, the output pulses from said clock being applied tosaid counter during the period of each command pulse, said counterhaving first and second outputs representing first and second periods oftime, each substantially greater than said coded duration;

first and second AND gates, each having first and second inputs, saidfirst inputs of said first and second AND gates being connected,respectively, to said first and second outputs of said counter, saidsecond input of said first and second AND gates being supplied with saidshort duration pulses whereby an output is developed at the output ofone of said first or second gates when a command pulse of saidpredetermined durations is counted by said counter, said output fromsaid AND gates serving to provide first and second functions.

7. The invention as defined in claim 6 wherein said pulse shift registerand said timing shift register are reset whenever said command pulses orspaces are different from said coded durations.

8. In a signaling system having signal transmitting means at a centralstation for transmitting coded address and command signals to remotestations, and a command signal decoder at each of said remote stationsfor decoding said command signals, said command signal and said addresssignals each comprising a plurality of signal pulses and spaces eachhaving a coded duration, the first pulse of said address signalimmediately following the last space of said command signal, saidcommand decoder comprising:

means for generating a short duration pulse at the leading and trailingedges of each of said signal pulses;

means for generating a short duration pulse at the leading and trailingedges of each of said signal pulses;

a clock for generating timing pulses, said clock being synchronized bysaid short duration pulses;

a timing shift register having a plurality of outputs, each of saidoutputs representing one possible coded duration, said timing shiftregister being advanced by the timing pulses of said clock;

a pulse shift register having a plurality of outputs equal to the numberof pulses and spaces of said command signal, said pulse shift registerbeing advanced by each of said short duration pulses whereby each outputrepresents a particular pulse or space; and

a system of gates, a selected one of said gates being enabled inresponse to one preselected combination of the outputs of said pulseshift register and said timing shift register, and a response to saidaddress signal.

9. The invention as defined in claim 8 wherein said command decoder alsocomprises first and second gates, the output from said gates serving toinitiate or terminate a function, said first gate being enabled when theduration of said command signal is equal to a predetermined period oftime substantially greater than said first coded duration, said secondgate being enabled when the duration of said command signal pulse isequal to a second such predetermined period of time, whereby a functionmay be performed at all remote stations simultaneously.

10. The invention as defined in claim 8 wherein said command decodercomprises a counter, the output pulses from said clock being applied tosaid counter during the period of each command pulse, said counterhaving first and second outputs representing first and second periods oftime, each substantially greater than said coded duration;

first and second AND gates, each having first and second inputs, saidfirst inputs of said first and second AND gates being connected,respectively, to said first and second outputs of said counter, saidsecond input of said first and second AND gates being supplied with saidshort duration pulses whereby an output is developed at said first orsecond output when a command pulse of said predetermined durations iscounted by said counter, the output from said AND gates serving toprovide first and second functions.

l l. The invention as defined in claim wherein said pulse shift registerand said timing shift register are reset whenever said command pulses orspaces are different from said coded durations.

12. In a signaling system having a central station and a plurality ofremote stations, said central station having means for sequentiallytransmitting time coded address signals to each of said remote stationsin a preestablished sequence, each of said remote stations transpondingto said central station upon receipt of a respective time coded addresssignal, the combination comprising:

a fixed frequency oscillator having a fixed frequency output;

a gate having an output terminal and first and second input terminals,said fixed frequency output being applied to the first input terminal,said fixed frequency output being coupled to said remote stationsthrough the output terminal of said gate when said gate is enabled, saidgate being enabled when an enabling pulse is applied to said secondterminal, the duration of each enabling pulse establishing said timecoded address signals;

first enabling pulse generating means for sequentially generatingenabling pulses of different durations, said durations representing saidcoded address signals, the output of said enabling pulse generatingmeans being applied to said second terminal;

a first plurality of duration determining means connectable into saidenabling pulse generating means for establishing the duration of saidenabling pulse;

sequential switching means for sequentially connecting each of saidduration determining means into said enabling pulse generating means forestablishing the durations of said enabling pulse in said preestablishedsequence;

a second plurality of selectable duration determining means;

second enabling pulse generating means for sequentially generatingenabling pulses of different durations distinct from the durations ofsaid coded address signals, said distinct durations repesenting acommand signal;

means for interrupting said first enabling means and for applying saidsecond enabling means to said second input terminal for transmitting acommand signal to said remote station;

means after the transmission of said command for transmitting a codedaddress signal;

means at said remote stations for decoding said command signal;

means at said remote station for decoding said address signal; and

means responsive to the decoding of said address signal for generating aresponse to said command.

1. In a signaling system having a central station and a plurality ofremote transponding stations, the combination comprising: signaltransmitting means at said central station for transmitting codedaddress signal to said remote stations; an address decoder at each ofsaid remote stations for decoding a particular one of said coded addresssignals; means responsive to the decoding of a particular one of saidaddress signals for generating a response signal to said centralstation; command means at said central station for transmitting a codedcommand signal ahead of a selected address signal; a command decoder ateach of said remote stations for decoding said command signals; andmeans responsive to the decoding of said command signals and thegeneration of said response signal for generating a response to saidcommand signal.
 2. The invention as defined in claim 1 wherein saidsignal transmitting means transmits said coded address signals in apreestablished sequence; and wherein said command transmitting meansincludes means for interrupting and delaying said sequence until thetransmission of said command signal and a selected address signal arecompleted.
 3. The invention as defined in claim 2 wherein said addressand command signals are duration coded pulses, said command decodercomprising a plurality of gates, said plurality being equal to thenumber of command signals, said gates each having an output connected toa respective load and having first and second inputs, each of said firstinputs being supplied with a pulse by only one decoded command signal,said second input being enabled by said response signal.
 4. Theinvention as defined in claim 1 wherein said command signal and saidaddress signal each comprises a plurality of pulses and spaces eachhaving a coded duration, the first pulse of said address signalimmediately following the last space of said command signal, and whereinsaid command decoder comprises: means for generating a short durationpulse at the leading and trailing edges of each of said pulses; a clockfor generating timing pulses, said clock being synchronized by saidshort duration pulses; a timing shift register having a plurality ofoutputs, each of said outputs representing one possible coded duration,said timing shift register being advanced by the timing pulses of saidclock; a pulse shift register having a plurality of outputs equal to thenumber of pulses and spaces of said command signal, said pulse shiftregister being advanced by each of said short duration pulses wherebyeach output represents a particular pulse or space; and a system ofgates, a selected one of said gates being enabled in response to onepreselected combination of the outputs of said pulse shift register andsaid timing shift register, and a response to said address signal. 5.The invention as defined in claim 4 wherein said command decoder alsocomprises first and second gates, the outputs from said gates serving toinitiate or terminate a function, said first gate being enabled when theduration of said command signal is equal to a first predetermined periodof time substantially greater than said coded duration, said second gatebeing enabled when the duration of said command signal pulse is equal toa second such predetermined period of time, whereby a function maysimultaneously be performed at all remote stations.
 6. The invention asdefined in claim 4 wherein said command decoder also comprises acounter, the output pulses from said clock being applied to said counterduring the period of each command pulse, said counter having first andsecond outputs representing first and second periods of Time, eachsubstantially greater than said coded duration; first and second ANDgates, each having first and second inputs, said first inputs of saidfirst and second AND gates being connected, respectively, to said firstand second outputs of said counter, said second input of said first andsecond AND gates being supplied with said short duration pulses wherebyan output is developed at the output of one of said first or secondgates when a command pulse of said predetermined durations is counted bysaid counter, said output from said AND gates serving to provide firstand second functions.
 7. The invention as defined in claim 6 whereinsaid pulse shift register and said timing shift register are resetwhenever said command pulses or spaces are different from said codeddurations.
 8. In a signaling system having signal transmitting means ata central station for transmitting coded address and command signals toremote stations, and a command signal decoder at each of said remotestations for decoding said command signals, said command signal and saidaddress signals each comprising a plurality of signal pulses and spaceseach having a coded duration, the first pulse of said address signalimmediately following the last space of said command signal, saidcommand decoder comprising: means for generating a short duration pulseat the leading and trailing edges of each of said signal pulses; meansfor generating a short duration pulse at the leading and trailing edgesof each of said signal pulses; a clock for generating timing pulses,said clock being synchronized by said short duration pulses; a timingshift register having a plurality of outputs, each of said outputsrepresenting one possible coded duration, said timing shift registerbeing advanced by the timing pulses of said clock; a pulse shiftregister having a plurality of outputs equal to the number of pulses andspaces of said command signal, said pulse shift register being advancedby each of said short duration pulses whereby each output represents aparticular pulse or space; and a system of gates, a selected one of saidgates being enabled in response to one preselected combination of theoutputs of said pulse shift register and said timing shift register, anda response to said address signal.
 9. The invention as defined in claim8 wherein said command decoder also comprises first and second gates,the output from said gates serving to initiate or terminate a function,said first gate being enabled when the duration of said command signalis equal to a predetermined period of time substantially greater thansaid first coded duration, said second gate being enabled when theduration of said command signal pulse is equal to a second suchpredetermined period of time, whereby a function may be performed at allremote stations simultaneously.
 10. The invention as defined in claim 8wherein said command decoder comprises a counter, the output pulses fromsaid clock being applied to said counter during the period of eachcommand pulse, said counter having first and second outputs representingfirst and second periods of time, each substantially greater than saidcoded duration; first and second AND gates, each having first and secondinputs, said first inputs of said first and second AND gates beingconnected, respectively, to said first and second outputs of saidcounter, said second input of said first and second AND gates beingsupplied with said short duration pulses whereby an output is developedat said first or second output when a command pulse of saidpredetermined durations is counted by said counter, the output from saidAND gates serving to provide first and second functions.
 11. Theinvention as defined in claim 10 wherein said pulse shift register andsaid timing shift register are reset whenever said command pulses orspaces are different from said coded durations.
 12. In a signalingsystem having a central station and a plurality of reMote stations, saidcentral station having means for sequentially transmitting time codedaddress signals to each of said remote stations in a pre-establishedsequence, each of said remote stations transponding to said centralstation upon receipt of a respective time coded address signal, thecombination comprising: a fixed frequency oscillator having a fixedfrequency output; a gate having an output terminal and first and secondinput terminals, said fixed frequency output being applied to the firstinput terminal, said fixed frequency output being coupled to said remotestations through the output terminal of said gate when said gate isenabled, said gate being enabled when an enabling pulse is applied tosaid second terminal, the duration of each enabling pulse establishingsaid time coded address signals; first enabling pulse generating meansfor sequentially generating enabling pulses of different durations, saiddurations representing said coded address signals, the output of saidenabling pulse generating means being applied to said second terminal; afirst plurality of duration determining means connectable into saidenabling pulse generating means for establishing the duration of saidenabling pulse; sequential switching means for sequentially connectingeach of said duration determining means into said enabling pulsegenerating means for establishing the durations of said enabling pulsein said pre-established sequence; a second plurality of selectableduration determining means; second enabling pulse generating means forsequentially generating enabling pulses of different durations distinctfrom the durations of said coded address signals, said distinctdurations repesenting a command signal; means for interrupting saidfirst enabling means and for applying said second enabling means to saidsecond input terminal for transmitting a command signal to said remotestation; means after the transmission of said command for transmitting acoded address signal; means at said remote stations for decoding saidcommand signal; means at said remote station for decoding said addresssignal; and means responsive to the decoding of said address signal forgenerating a response to said command.